Design for Testability Implementation Of Dual Rail Half Adder Based on Level Sensitive Scan Cell Design

Design for testability (DFT) refers to hardware design styles or it is an added hardware that reduces test generation complexity and test cost, also increases test quality. Sleep Convention Logic (SCL) is an asynchronous logic style which is based on Null Convention Logic (NCL). In the SCL the combinational blocks are made of threshold gates. SCL utilizes power gating method to further reduce the power consumption by incorporating the sleep signal in every single gate. There are currently no DFT methodologies existing for SCL. But in the current NCL, specific DFT methods cannot be directly used due to the sleep mechanism for power gating. The aim of this paper is to analyze various stuck-at-faults within SCL pipelines. Hence by using scan based testing methodology the SCL circuit is analyzed at the cost of usual area overhead .The proposed methodology is based on fault analysis. Keywords— sleep convention logic, null convention logic, dual rail, power gating technique, Design for testability.